Miniaturization is a driving force to improve device performance and reduce cost for chip manufacturing. Current lithographic techniques are based on a “top-down” approach, wherein patterns are imaged onto a resist via optical projection through a predefined mask. However it is becoming increasingly difficult and expensive to extend this approach to create patterns with dimensions on the nanometer scale. Accordingly, there exists a need for a practical and economical approach to create patterns with dimensions on the nanometer scale.